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| Document_Type | Document Link | Link_Type |
| Software | Verilogger Pro | 4shared |
| Software | Verilog Library | direct |
| Slides |
PowerPoint presentation used in first session. | direct |
| Slides |
D. Hyde, Handbook on Verilog HDL | direct |
| Datasheets | PIC Datasheet | direct |
| Past Paper | Design-Lab-Mid-Exam.pdf | direct |
| Lab Experiments | REPORTS AND PRELABS.rar | direct |
| Lab Experiments | Structural Modules.rar | direct |
| Lab Experiments | behavioural Modules.rar | direct |
| Lab Experiment |
Experiment 1: Introduction to Verilog - SR Latch | direct |
| Lab Experiment |
Experiment 2: 8-bit Adder/Subtractor | direct |
| Lab Experiment | Experiment 3 : 8-bit ALU | direct |
| Lab Experiment | Experiment 4: Datapath | direct |
| Lab Experiment | Experiment 5: Program Memory | direct |
| Lab Experiment | Experiment 6: Data Memory | direct |
| Lab Experiment | Experiment 7: Data Memory - Part II | direct |
| Lab Experiment | Experiment 8: The Processor Module | direct |
| Lab Experiment | Experiment 9: The Control Module | direct |
| Lab Experiment | Experiment 10: Full Processor Simulation | direct |
| Software | TinyCAD | Sourcefroge |
| Lab Experiment | Lab Experiments (Spring 2010) | direct |
| Quiz | Quiz 1 (Spring 2010) | direct |
| Quiz | Quiz 2 (Spring 2010) | direct |
